Computer and PC Design

Home Admissions Course Guide Computer and PC Design

This Course Guide has been taken from the most recent presentation of the course. It would be useful for reference purposes but please note that there may be updates for the following presentation.


Computer and PC Design

ELEC S333 Computer and PC Design is a two-semester, ten-credit course for the BSc/BSc(Hons) in Computer Engineering. The study units, web resources, and activities and self-tests will help you master the topics over a period of around 40 weeks.

The course is about high performance computer architecture, and how it is implemented in various contemporary computers, including the PC. The computer architectures we will cover are mature, proven technologies. These high performance computer design techniques were mainly used in mainframe computers many years ago. As semiconductor technology progressed, however, these designs gradually found their way into small computers. The theoretical aspects of computer architecture are supplemented with example products. We will rely on materials on the Internet for many of these examples.

The course aims to provide you with in-depth knowledge of computer architecture, with relevant issues in PC design and operating systems. You will also be exposed to a range of design techniques and performance measurements.

At the end of the course, you should be able to:

  1. Diagnose the key concepts in computer and PC design through case studies;
  2. Discuss the details of instruction set architecture, including the classification of instruction sets, the roles of the operator and operand, the macro-and-micro fusion of instructions, and the uses of various addressing modes;
  3. Analyse the different stages of single cycle datapaths, and apply these concepts to the pipelining process and parallelism in order to improve system performance;
  4. Evaluate and review the range of pipeline hazards and problems induced by parallelism, and illustrate the respective techniques to enhance processor performance through exploiting idle resources and additional hardware;
  5. Explore the performance-related tradeoffs in the design of memory hierarchy in computer architecture, including basic cache and memory designs, and appraise various technologies and standards that are employed by today's computer system manufacturers;
  6. Appraise the mechanisms for connecting external devices to the computer system, including the local and external system, such as SSD; and
  7. Analyse the impact of different technologies, such as multi-core architecture, Ivy bridge, SIMD, GPU architecture, and VT in computer processor design and development, and assess the architectures in common commercial processors for different applications such as PCs, servers and mobile devices via case studies.

Course organization

The following chart gives a general overview of the course structure.


UnitNo. of weeksAssessment
1Computer designs and performance2 
2Instruction set architecture4Assignment 1
3Parallelism and dependences6 
4Exploiting parallelism6Assignment 2
5Boosting performance in processors6 
6Memory hierarchy and designs6Assignment 3
7Peripherals and buses5 
8Exploiting enhancements to processor technologies3Assignment 4

Study units

Units 18 are the main teaching components of the course. The following are brief overviews of each unit:


Unit 1 Computer designs and performance

This unit introduces the factors which contribute to computer performance, as well as the common metrics and tools for evaluating computer performance. Students will be introduced to the ways of classifying and analysing computer system performance, the indices including CPI, MIPS, FLOPS, MemBench and TPC, and the considerations for choosing performance benchmarks and tools.


Unit 2 Instruction set architecture

This unit first reviews computer hardware performance and explains how software runs in the hardware. It then introduces the various instruction set architectures, discussing the different roles of the operators, operands, stack, accumulator, and register-memory. By referring to programming examples, the unit describes and compares different data addressing modes and control flows. A comparison between CISC and RISC architectures is then given, followed by related case studies. The unit ends with a discussion on instruction set encoding and the roles of compilers.


Unit 3 Parallelism and dependences

This unit first gives an introduction to datapaths, followed by descriptions of the stages in a single cycle datapath, including the Instruction Fetch stage, Instruction Decode / Register Fetch stage, Instruction Execution / Memory Address Calculation stage, Memory Access stage, and Register Write-back stage. It then presents ways of integrating and evaluating the stages, and explains how hardware designs can be used to support different addressing modes. The second part of the unit discusses how multicycle datapaths and pipelining can lead to improved performance in RISC- and CISC-based processors, as well as in more complex architectures. Finally, pipeline hazards, microinstructions, and other pitfalls in pipelines are outlined.


Unit 4 Exploiting parallelism

This unit expands on the concepts learned in the previous unit, and focuses on the details of instruction level parallelism. Data dependence, name dependence, control dependence, loop-carried dependence and structural hazards are all described. The unit then discusses how these dependences can be reduced by means such as loop unrolling, software pipelining, data forwarding, register renaming, branch prediction buffer, and branch target buffer. The unit concludes with case studies to illustrate how instruction level parallelism is implemented.


Unit 5 Boosting performance in processors

This unit first describes the nature of structural hazards, and discusses the use of dynamic pipelining and out-of-order instructions for avoiding structural hazards. It then presents different ways of boosting the performance of processors. Hardware-level promotion of parallelism, including superscalar architecture, hyper-threading architecture, and vector processors are discussed. Design issues of multi-processors are then discussed, with an emphasis on distributed memory multiprocessor architecture, multiprocessor cache coherence, centralized shared-memory architecture, and multi-core processor architecture. The unit concludes by discussing the main bottlenecks for enhancing processor performance.


Unit 6 Memory hierarchy and designs

The concepts and rationales of data localities and memory hierarchy are given. The unit then describes the different types of main memory, including DRAM, SRAM, SDRAM, DDR memory, as well as virtual memory, and NAND-based flash memory. The design and performance optimization of a cache in a computer system is then discussed. The unit concludes by giving examples of memory management at different hierarchies.


Unit 7 Peripherals and buses

This unit first explains the roles of buses in a computer system, describes the bus mastering mechanism and the role of the chipset. It then describes how the peripherals are accessed at different levels from the BIOS to operating system. The second half of the unit gives an overview of different external buses, including universal serial bus, SATA, SCSI and solid state memory interface, as well as internal buses, including south bridge components, PCI, PCI-X and PCI Express.


Unit 8 Exploiting enhancements to processor technologies

This unit presents recent technologies for enhancing processor performance. The technologies and techniques discussed include the Graphical Processing Unit (GPU), Single Instruction Multiple Data (SIMD) instruction set for multimedia, tri-gate technology, Sandy Bridge, Ivy Bridge, multi-processor and multi-core systems, grid computing, cloud computing, super computers, virtualization technologies, and processors for mobile devices. The unit concludes by discussing the emerging trends in computer and processor design.


Equipment required

A computer system to access the Internet for the online components is required for this course. The minimum configuration of the computer system is:

  • Pentium 4 or above with 2GB RAM
  • Microsoft Windows Vista or higher
  • VGA display card and Colour monitor
  • 10 GB free space hard disk
  • CD-ROM Drive (16X or better), sound card and speaker
  • LAN card for broadband

There will be four assignments, and one three-hour final examination. The best three out of four assignments will be counted for assessment.


Assessment typeMarks
Assignment 116.7%
Assignment 216.7%
Assignment 316.7%
Assignment 416.7%


There will be both face-to-face tutorials and online tutor support.



There are twenty hours of face-to-face tutorials.


Online support

The online platform is the standard HKMU OLE based on Lotus Domino. The most important support components are the discussion board and the assignment record and extension system.

Coming soon